Circuit configuration of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
CML based DFF combined with NAND function used in 4/5 prescaler block | Download Scientific Diagram
High Speed Digital Blocks
High speed CML latch using active inductor in 0.18μm CMOS technology | Semantic Scholar
ECEN620: Network Theory Broadband Circuit Design Fall 2022
KR100682266B1 - Differential output tspc d-type flip flop and frequency divider using it - Google Patents
Performance evaluation of the low-voltage CML D-latch topology - ScienceDirect
adding reset function to D Flip FLOP | Forum for Electronics
Figure 5.21 from Cmos Logic and Current Mode Logic 5.1 Introduction | Semantic Scholar
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
Analysis and Design of High-Speed CMOS Frequency Dividers
Current-Mode-Logic (CML) Latch | EveryNano Counts
Asynchronous Primitives in CML - ppt download
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
PDF) Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices